Article ID: 000084908 Content Type: Troubleshooting Last Reviewed: 09/12/2012

Why does my PCI Express endpoint not respond to the Link Disable request from the root complex?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may experience problems commanding the Altera® PCI Express® core to the Link Disable state, when configured as an endpoint.  The PCI Express core may transmit a truncated (incorrect length) TS1 message during the transition to Electrical Idle.

In simulation, your Root Port BFM may complain about a "TS Ordered set length error".

Resolution

The workaround at this time is to avoid using this optional feature.

Related Products

This article applies to 3 products

Arria® II GX FPGA
Cyclone® IV GX FPGA
Stratix® IV GX FPGA