Article ID: 000084858 Content Type: Troubleshooting Last Reviewed: 12/31/2014

Some 100G Interlaken IP Core Parameter Settings Cause Arria 10 Timing Issues

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

If your 100G Interlaken IP core instance targets an Arria 10 device, and you turn on either of these two parameters in the 100G Interlaken parameter editor, your IP core might not achieve timing closure in compilation.

  • Include advanced error reporting and handling
  • Enable M20K ECC support
Resolution

This issue has no workaround. To avoid timing issues in the 14.0 Arria 10 Edition version of this IP core, you should turn off these two parameters.

This issue is fixed in version 14.1 of the 100G Interlaken IP core.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.