Check with your simulation tool vendor for details on whether the tool can model this.
Article ID: 000084780 Content Type: Troubleshooting Last Reviewed: 09/11/2012
Does my FPGA IBIS model accurately reflect the duty cycle distortion of my FPGA output signal?
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Description The IO buffer model will accurately reflect the duty cycle distortion that is caused by the buffer itself. However, the buffer model does not represent any DCD on the signal that feeds into the output buffer. Because the output buffer may have a signal fed from any sources, the simulation model has no concept of the magnitude of the DCD as it feeds in.