Article ID: 000084763 Content Type: Troubleshooting Last Reviewed: 08/29/2012

If I am using the top ATX PLL in the bank and the ATX PLL supports the data rate for Stratix® V, can I ignore Critical Warning for ATX PLL Range?

Environment

  • Stratix® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, you can ignore the warning. When you are using the top ATX PLL in the bank for Stratix® V and the ATX PLL supports the data rate, Quartus®II also maybe shows a Critical Warning. It is to remind you some ATX PLL locations or some speed grade devices can’t support the VCO frequency. The following shows the Critical Warning.

 

Critical Warning (11107): ATX PLL node "low_latency_serdes:inst|altera_xcvr_low_latency_phy:low_latency_serdes_inst|sv_xcvr_low_latency_phy_nr:sv_xcvr_low_latency_phy_nr_inst|sv_xcvr_10g_custom_native:sv_xcvr_10g_custom_native_inst|sv_xcvr_plls:sv_xcvr_native_insts[0].gen_bonded_group_plls.gen_tx_plls.tx_plls|pll[0].pll.atx_pll.tx_pll" uses a VCO frequency that is not currently supported.  Please see documentation for StratixV specifications.

 

This problem maybe is found in Quartus® II software version 12.0cb/12.0_174/12.0_178 and it is scheduled to be fixed in a future release of the Quartus® II software version

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