Article ID: 000084672 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why doesn't the Soft IP PCIe* core send my Avalon®-MM memory read request to PCIe* bus?

Environment

  • Stratix® IV GT FPGA
  • Stratix® II GX FPGA
  • Stratix® IV GX FPGA
  • Arria® II GX FPGA
  • Stratix® GX FPGA
  • Cyclone® IV GX FPGA
  • Arria® GX FPGA
  • Quartus® II Subscription Edition
  • IP_Compiler for PCI Express
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    Description

    Due to a bug in Soft IP PCIe* generated by SOPC builder, the core may not send memory read request (MRD) to PCIe* bus although it is presented correctly on Avalon®-MM interface.

    This issue does not affect Soft IP with Avalon®-ST interface or any Hard IP PCIe* cores.

    If you are using Quartus® II software version 10.1, you can download download and install the following patch to resolve this issue.

    Currently there is no workaround for earlier Quartus® II software versions. If using an earlier version of the Quartus® II tools, Intel® recommend moving to Quartus® II version 11.0 software.

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