Article ID: 000084671 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do Stratix II GX HSPICE models include REFCLK pin models, If not, how can I simulate the REFCLK pin?

Environment

  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    We do not have HSPICE or IBIS models for the transceiver REFCLK pins in Stratix® II GX device. 

    Using the HSSI RX pin model should be sufficient to simulate the REFCLK pin.  You will not be able to model the signal as it passes through the REFCLK buffer.

    There are no plans to add REFCLK pin models for Stratix II GX or future high speed transceiver devices.

    Related Products

    This article applies to 8 products

    Stratix® II GX FPGA
    Arria® II GX FPGA
    Arria® II GZ FPGA
    Cyclone® IV GX FPGA
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® V GX FPGA
    Stratix® V GS FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.