Article ID: 000084661 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why does my third-party PCI Express Bus Functional Model (BFM) flag an invalid symbol after the End of Data Stream (EDS) token?



The Arria® V GZ and Stratix® V Hard IP for PCI Express® may cause third-party BFMs to flag invalid symbols after EDS for the following reason:

When the Hard IP for PCI Express enters hot reset, the Link Training Status State Machine(LTSSM) first passes through the Recovery states. When in recovery. Idle, it starts a data stream; before entering the Hot Reset state, the IP sends EDS to end the Data Stream.

Per the PCI Express specification, the Hard IP should send EIEOS after EDS, but it does not. The Hard IP follows EDS with a TS1 with the hot reset bit set. 

This issue can be seen in simulation. No impact has been observed in actual hardware testing.



Ignore the error from your third-party BFM.

Related Products

This article applies to 5 products

Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® V GZ FPGA