Article ID: 000084619 Content Type: Error Messages Last Reviewed: 10/30/2015

Error (18218): Attempted to fit <n> IOPLL merge groups in <fewer than n> locations

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If a design targeting an Arria® 10 device instantiates more I/O phase lock loops (PLLs) than the number of I/O PLL resources available on the device, the Quartus® Prime software issues an error. The number of I/O PLLs indicated in the error message depends on the Altera® IP in your design, and this number might be greater than the number of I/O PLLs recorded in the Analysis and Synthesis report.

    For example, the External Memory Interface (EMIF) IP uses one I/O PLL for every I/O bank it occupies. The Fitter determines the actual number of I/O PLLs that the design consumes based on the pin-out requirement. If the number of I/O PLLs determined by the Fitter exceeds the number of available I/O PLLs on the device, an error occurs.

    Other examples of Altera IP that consume I/O PLLs include Low Latency 40- and 100-gigabits per second Ethernet (GbE) IP core, Altera LVDS SERDES IP core, Altera PHYLite IP cores, and SerialLite III Streaming IP core.

    Resolution

    Reduce the number of I/O PLLs in your design. Altera recommends the following strategies:

    • Convert some of the I/O PLL IP in your design into integer-mode fractional PLL (fPLL) IP.
    • EMIF, LVDS SERDES, and PHYLite are I/O PLL-consuming Altera IP cores that can generate additional core clocks for use. If your design contains these IP cores, consider generating additional core clocks to reduce I/O PLL demand. In the IP parameter editor, choose the Specify additional core clocks based on existing PLL option under the General tab.
    • Modify the pin-out of an EMIF IP to use fewer I/O banks. For a given configuration, the EMIF IP parameter editor reports the fewest I/O banks possible. Refer to the General Pin-Out Guidelines for Arria 10 EMIF IP section in the External Memory Interface Handbook Volume 2: Design Guidelines for more information.
    • Enable the TX PLL sharing option in the Ethernet IP to allow multiple Ethernet instances to share a single I/O PLL. For example, in the Low Latency 40- and 100-GbE IP parameter editor, choose the Use external TX MAC PLL option under the Main tab. Refer to the External TX MAC PLL section in the Low Latency 40- and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide for more information.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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