Article ID: 000084506 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Does the Stratix™ family provide controlled on-chip termination?

Environment

  • I O
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, the Stratix family provides controlled, on-chip termination for the following:

    • Driver impedance matching (LVTTL, LVCMOS)
    • Driver series termination (SSTL3, SSTL2)
    • Parallel near-end termination (HSTL2, GTL, GTL )
    • Parallel far-end termination (SSTL, HSTLI, GTL, GTL , CTT)
    • Differential far-end termination (LVDS only)

    Two pins per I/O bank are tied to reference resistors. Specifically, RUP/RDN connect through resistance to VCC/GND.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs

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