Article ID: 000084447 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why does my project with an RLDRAM or QDR interface stall in the fitter?

Environment

    Quartus® II Software
    RLDRAM 3 UniPHY Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software, the compilation may never finish during the fitter stage if you let the Quartus® II software auto-place the pins. This issue is caused by the fitter placing multiple strobe pins or data mask (DM) pins from different interfaces into the same x4 DQ/DQS group when using RLDRAM II, RLDRAM III, QDR, or QDR II.

Resolution

To work around this issue, manually place the strobe pins and DM pins into different x4 DQ/DQS groups.

This issue has been fixed in the Quartus® II software version 13.0.

Related Products

This article applies to 18 products

Arria® II GX FPGA
Arria® II GZ FPGA
HardCopy™ IV GX ASIC Devices
Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
HardCopy™ III ASIC Devices
HardCopy™ IV E ASIC Devices
Arria® V GZ FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® V GT FPGA
Arria® V GX FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.