Article ID: 000084426 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does Quartus II synthesis incorrectly process bit selects from signed variables?



The Quartus® II software version 6.0 and 6.0 SP1 incorrectly process bit selects from signed variables due to a known software problem. Verilog code involving bit selects from signed variables should return unsigned values as specified in the Verilog LRM (Std 1364-2001 Version C, Sec 4.5.1).

This problem does not exist in versions 5.1 or earlier. The problem is fixed beginning with the Quartus II software version 6.1.

As an example of this problem, the Quartus II software version 6.0 incorrectly processeses the following code sample:

reg [7:0] unrounded;

reg [6:0] rounded;

always @ (posedge clk) begin

 rounded <= unrounded[7:1]   unrounded[0];

The software should zero-extend the signal unrounded[0] to ensure that the one bit value is added to the bit slice of unrounded[7:1].

The Quartus II software versions 6.0 and 6.0 SP1 sign-extend the signal unrounded[0] instead of zero-extending the signal. In the example, if the unrounded[0] signal is a 1 value, the software interprets the 1 as the sign of the number, and therefore converts it into a 7 bit signed representation of -1 instead of an unsigned value. Therefore, the software adds -1 to unrounded[7:1], instead of adding 1.

To avoid this problem (in versions 6.0 or 6.0 SP1), do one of the following:

  • Contact mySupport to request patch 1.20 for the Quartus II software version 6.0 SP1.  
  • Put parentheses around one of the variables and force the entire expression to evaluate as unsigned using the Verilog-2001 function :
  • rounded <= (unrounded[7:1])   unrounded[0]
  • Manually pad the leading zeros as follows (i.e. explicitly state the leading bits should be 0):
  • rounded <= unrounded[7:1]   {{6{1'b 0}}, unrounded[0]};


Related Products

This article applies to 1 products

Stratix® II FPGAs