Article ID: 000084305 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why are the values for FS (Full Swing) and LF (Low Frequency) zero when simulating a PCIe Hard IP core for Gen3?

Environment

    Quartus® II Subscription Edition
    Simulation
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Description

There is an issue with the PCIe® Hard IP simulation models when targeting the Stratix® V and Arria® V GZ device families, where the values for FS and LF are zero for Gen3. Certain bus functional models (BFM) may report an error that FS and LF have values that violate the PCIe specification.

 

 

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 14.0.

Related Products

This article applies to 4 products

Arria® V GZ FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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