Article ID: 000084269 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any workarounds available if Quartus II software has previously allowed invalid pin placement of PCIe HIP?



Due to a bug in Quartus® II software 10.0sp1 and older versions, invalid pin location assignments for PCIe® HIP were permitted.

If PCIe HIP lane0 is incorrectly placed in a Physical Channel different than channel0 of Master Transceiver Block, the only available workarounds are:

1. Replace the HardIP with SoftIP
2. Respin the PCB with the corrected pin out
3. Attempt to utilize PCI Express "Lane Reversal" feature to enable a x1 configuration

If PCIe HIP is configured for x1 and Quartus II software 10.0 and previous version allows lane0 to be assigned to channel 1 of Master Transceiver block, the PCIe HIP will automatically use Lane Reversal feature and link up to x1 lane.

For Cyclone® IV GX software, if you have incorrectly placed x1 PCIe HIP with lane0 on channel1 and channel0 is not used or connected on your PCB, then simply regenerate the PCIe HIP core as a x2 interface with lane0 on channel 1 and lane 1 on channel 0. The core will then automatically down-train to a x1 interface using the lane reversal feature.

Quartus II software version 10.1 release and newer versions will error out if incorrect pin assignments are made.

Related Products

This article applies to 4 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA
Acex® 1K