Article ID: 000084260 Content Type: Troubleshooting Last Reviewed: 03/28/2014

Why does my PCI Express end point design, using legacy interrupts, send the "Deassert_INTA" message immediately after the “Assert_INTA” message, when signal Rxmirq_irq[n] is still asserted?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the PCI Express® core implementation in the Quartus® II software, the Deassert_INTA message may be sent out shortly after the Assert_INTA message, while the Rxmirq_irq[n] signal is still asserted.  This is not the intended operation of the legacy interrupt logic. 

    This issue affects designs implemented in Qsys, starting with Quartus II software version 11.0.

    To workaround this issue:

    1.       Download the following file:pciexp_dcram.v

    2.       Copy this file to the following directory in your Quartus II installation directory:  <install_dir>/ip/altera/ip_compiler_for_pci_express/lib

    3.       Regenerate the PCI Express core within Qsys

    4.       Regenerate the Qsys design

    5.       Recompile your project

    This issue will be fixed in a future release of the Quartus II software.

    Resolution This issue has been fixed in software release v11.1 and later

    Related Products

    This article applies to 7 products

    Cyclone® IV E FPGA
    Arria® II GZ FPGA
    Stratix® IV E FPGA
    Arria® II GX FPGA
    Cyclone® IV GX FPGA
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA

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