Article ID: 000084218 Content Type: Product Information & Documentation Last Reviewed: 01/01/2015

How can I enable interrupt support for the HLGPI[13:0] input only pins?

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    Description

     

    The HLGPI[13:0] input only pins of the Cyclone® V SX share pins with the HPS DDR controller. To identify the pin location for these GPI pins, see related solution.

    Physically the HLGPI[13:0] signals are connected to GPIO2_porta_input[13:26] in the HPS.  You can configure the HLGPI to generate interrupts just like other GPIO in GPIO2 component.  

    To configure the GPIO interrupts you will configure the following registers - gpio_inten, gpio_intmask, gpio_inttype_level, and the gpio_int_polarity registers.  These registers can be found in the address map for the Cyclone V HPS device at the following link:

    https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

     

    Related Products

    This article applies to 1 products

    Cyclone® V SX SoC FPGA

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