Error: add_fileset_file: No such file 15.0/ip/altera/merlin/altera_irq_clock_crosser/cadence/altera_irq_clock_crosser.sv while executing "add_fileset_file cadence/altera_irq_clock_crosser.sv SYSTEM_VERILOG_ENCRYPT PATH "cadence/altera_irq_clock_cros

Due to a problem in the Quartus® II software version 15.0, the altera_irq_clock_crosser fails to generate a VHDL simulation model and testbench. You may see the error below:

Error: add_fileset_file: No such file 15.0/ip/altera/merlin/altera_irq_clock_crosser/cadence/altera_irq_clock_crosser.sv    while executing"add_fileset_file cadence/altera_irq_clock_crosser.sv SYSTEM_VERILOG_ENCRYPT PATH "cadence/altera_irq_clock_crosser.sv" {CADENCE_SPECIFIC}"    (procedure "sim_vhdl" line 4)    invoked from within"sim_vhdl altera_irq_clock_crosser"

To work around this problem, manually update the following file, altera_irq_clock_crosser_hw.tcl, as follows:

1. Open< install_path>\ip\altera\merlin\altera_irq_clock_crosser\altera_irq_clock_crosser_hw.tcl in a text editor
2. Browse to proc sim_vhdl (line 56 in 15.0b129)
3. Remove the following two lines:
1.  add_fileset_file cadence/altera_irq_clock_crosser.sv SYSTEM_VERILOG_ENCRYPT PATH "cadence/altera_irq_clock_crosser.sv" {CADENCE_SPECIFIC}
2. add_fileset_file synopsys/altera_irq_clock_crosser.sv SYSTEM_VERILOG_ENCRYPT PATH "synopsys/altera_irq_clock_crosser.sv" {SYNOPSYS_SPECIFIC}
4. Save altera_irq_clock_crosser_hw.tcl and either re-open or refresh (F5) in Qsys

This problem will be fixed in future version of the Quartus II software.