The center PLLs at the bottom only have access to one PHYCLK network in the Stratix® V device.
Article ID: 000084178 Content Type: Troubleshooting Last Reviewed: 12/20/2013
Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device?
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Resolution If you need to use center PLLs to drive two external memory interfaces, use the PLL sharing mode.