Article ID: 000084075 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I create a testbench in VHDL or Verilog using ModelSim-Altera Wave editor?

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Description

This document describes the step-by-step process on how to create a VHDL or Verilog HDL testbench by creating test vector waveforms in the ModelSim-Altera Wave Editor.

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