Article ID: 000084047 Content Type: Troubleshooting Last Reviewed: 10/23/2015

What are the recommended board design guidelines to meet the MAX 10 JTAG port clock to output (tJPCO) specification?

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Description

With reference to Table 46 in the  MAX 10 FPGA Device Datasheet (PDF), the JTAG timing parameters for MAX® 10 devices are based on Cload = 10pF for TDO. 

To meet this Cload = 10pF specification, the trace length is required to be <= 2 inches between the JTAG driver component (e.g. micro-controller, processor or CPLD) and the MAX 10 devices JTAG interface. This is to ensure the JTAG timing is within specification. If the Cload value is over the 10pF spec, slow down the JTAG TCK frequency to ensure normal JTAG operation.

 

 

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Intel® MAX® 10 FPGAs

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