Article ID: 000083942 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Poll(interrupt) timeout


  • Intel® Quartus® Prime Pro Edition

    When multiple DMA handles are simultaneously opened with the Intel® FPGA Programmable Acceleration Card  N3000 factory image, you may get Poll(interrupt) timeout errors.

    The timeout errors are due to the factory image design having four DMA blocks sharing one interrupt.


    If your application requires multiple open DMA handles, then customize the AFU RTL design and software code as listed below:

    1. RTL design:

    In default file, line 257, dma_irq is sent to irq[0] of avmm_ccip_host_wr module. 

    .irq({3'b000, dma_irq}),

    Customize your design to map each irq from DMA blocks to a different bit.

    2. Software code:

    In fpga_dma.c file, line 701~702, fpgaRegisterEvent function uses 0 as fixed vector id.

    res = fpgaRegisterEvent(dma_h->fpga_h, FPGA_EVENT_INTERRUPT, dma_h->eh, 0 /*vector id */);

    Register different ids for your dma handles which are mapped to the irq bits in the RTL design.

    For example, to access DDRA and DDRB with two dma handles together, you can customize your RTL code to map dma_irq to irq[0] in afu_dma_0_inst for DDRA, and map dma_irq to irq[1] in afu_dma_1_inst for DDRB. In software code, use vector id 0 for dma handle 0 to access DDRA, use vector id 1 for dma handle 1 to access DDRB in fpgaRegisterEvent function.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® FPGA PAC N3000