Article ID: 000083940 Content Type: Troubleshooting Last Reviewed: 12/21/2018

Why do I see new non-SignalTap related hold violations after upgrading to the 1.1 Production (1.1 PV) release of the Intel® Programmable Acceleration Card (PAC) with Arria® 10 GX FPGA?


  • Intel® Quartus® Prime Pro Edition

    Hold time issues may be seen on Accelerator Functional Units (AFUs) developed using the PAC 1.1 PV release that were previously timing clean on the 1.1 Beta release. These occur because the source of the “afu_clk” changed from “clk1x” in 1.1 Beta to “clk100” in 1.1 PV. Due to an issue in 1.1 PV, the timing constraints were not updated to match a change in the input clock between 1.1 PV and 1.1 Beta, potentially leading to new hold timing violations being reported.


    To fix the issue, please modify the timing constraints for your custom AFU as shown in the example below. The sdc files for your AFU may reside within the hw/samples directory in the PAC software release directory hierarchy, or may alternatively reside in a custom location.

    Old (1.1 Beta): set_clock_groups -asynchronous \
    -group [get_clocks {*|dcp_iopll|dcp_iopll|clk1x}] \
    -group [get_clocks {*|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]

    New (1.1 PV): set_clock_groups -asynchronous \
    -group [get_clocks {*|dcp_iopll|dcp_iopll|clk100}] \
    -group [get_clocks {*|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]

    This change will only impact your custom AFU and will not impact any of the other design examples provided with the PAC 1.1 PV release.


    Related Products

    This article applies to 2 products

    Intel® Arria® 10 GX FPGA
    Intel® PAC with Intel® Arria® 10 GX FPGA