Article ID: 000083937 Content Type: Troubleshooting Last Reviewed: 12/31/2013

Why does the 'RX CDR PLL status' indicator show 'PLL not locked' on the Transceiver Toolkit when the 'RX CDR data status' indicator shows 'PLL locked' and data is being received correctly?

Environment

  • Arria® V GX FPGA
  • Arria® V GT FPGA
  • Stratix® V GT FPGA
  • Stratix® V GS FPGA
  • Stratix® V GX FPGA
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Description

The 'RX CDR PLL status' indicator showing 'PLL not locked' on the Transceiver Toolkit when the 'RX CDR data status' indicator shows 'PLL locked' is normal behavior.

  • The 'RX CDR PLL status' indicator displays the state of the transceiver rx_is_lockedtoref signal.
  • The 'RX CDR Data status' indicator displays the state of the transceiver rx_is_lockedtodata signal.

The Stratix® V GX handbook states "The Phase Frequency Detector (PFD) is inactive in LTD mode. The rx_is_lockedtoref status signal toggles randomly and is not significant in LTD mode.".

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