You may receive above error message when you use signal compiler block to compile the FFT Megacore ® design with MAX 10 devices in DSP Builder software tool.
Here are the steps to work around this issue:
1. Open \'Advanced\' tab of Signal Compiler
2. Click on \'Analyze\'. This stage analyzes DSP builder standard blockset design and creates Quartus® II project. Please ignore the error reported at this stage.
3. Edit the <model_name>.qsf file that located at <model_name>_dspbuilder directory that has been created at the same level where the model file is.
a) Change MAX 10 FPGA to just MAX 10
B) add set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM"
4. Go back to Signal Compiler and run \'Synthesis\' and \'Fitter\' steps to complete Quartus compilation.
This issue will be fixed in a future version of the Quartus II software.
