Article ID: 000083766 Content Type: Error Messages Last Reviewed: 08/14/2012

Error: Pin termination_blk0~_rup_pad is incompatible with I/O <I/O bank>. It uses I/O standard <I/O voltage> which has VCCIO requirement of <I/O voltage>.

Environment

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Description

You may receive error messages for designs that target Arria® II GX devices when migrating from versions of the Quartus® II software prior to 11.0 to version 11.0 or later if you have location assignments made to the calibrated on-chip termination (OCT) control blocks.

Prior to version 11.0, there was a mis-match in the naming of the RUP and RDN pins with respect to their termination blocks.  For example, pins RUP0 and RDN0 were connected to the internal termination block named "termination_blk1", while pins RUP1 and RDN1 were connected to the internal termination block named "termination_blk0".

Beginning with Quartus II version 11.0, the internal names of the termination blocks were changed to match their respective RUP and RDN pin names.

If your design allows the Quartus II software to auto place the RUP and RDN pins for the I/O pins that use calibrated OCT, then you will not be affected by this issue.  If however you have I/O standard or location assignments made to the termination_blk instances, you will need to change the assignments to be compatible with the new naming conventions used beginning in version 11.0 of the Quartus II software.

Related Products

This article applies to 1 products

Arria® II GX FPGA

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