Article ID: 000083707 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the difference between afi_rdata_en and afi_rdata_en_full signals in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The difference between afi_rdata_en and afi_rdata_en_full is that you can use afi_rdata_en to mask off any beat coming back from the memory but you have to keep afi_rdata_en_full asserted for the full length of your read.

For example, if you have a burst of 8 on memory side, which takes 4 clock cycles, you have to keep afi_rdata_en_full asserted for all 4 cycles (i.e. 1111) but if you want to mask off words 5 and 6 out of the 8 words that are coming back, you can go ahead and make afi_rdata_en 1101 and you will only read back words 1, 2, 3, 4, 7 and 8 because 5 and 6 will be masked off.

Related Products

This article applies to 5 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.