Article ID: 000083704 Content Type: Troubleshooting Last Reviewed: 01/20/2016

Why am I still getting a Critical Warning about Simultaneous Switching Noise (SSN) and crosstalk even though I am following the SSN and crosstalk reduction guidelines?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1 you may see the critical warning shown below, even though you have followed the Knowledge Base solution ID: rd10102013_979 

    Critical Warning (12888): Cross talk of LVDS Pin <design_pin_name> from SE I/O is too high. Reassign or move one or more of the following SE I/Os pins location and re-run the analysis again.  Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of crosstalk for the following SE I/O pins does not exceed 100%.

    This error may incorrectly appear under these conditions:

    - When using a single ended IO standard other than 2.5V within the same or across different I/O banks with LVDS pins.
    - When using 2.5V single ended IO across different I/O bank with LVDS pins.

    Resolution

    If you have identified that a warning is invalid, you can temporarily disable the critical warning by adding the following line in your .qsf file.

    set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to <design_pin_name>

    This problem will be fixed in future release of the Quartus II software.

    Related Products

    This article applies to 6 products

    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA