Article ID: 000083674 Content Type: Troubleshooting Last Reviewed: 07/28/2015

SPI Slave to Avalon Master Bridge data loss

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software, the SPI Slave to Avalon® Master Bridge IP, may drop data under heavy load.
    Resolution

    To workaround this problem, replace the generated synthesis/submodules/spiphyslave.v file with this file: spiphyslave.v

    This problem is scheduled to be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 37 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Cyclone® IV E FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Cyclone® FPGAs
    Cyclone® III LS FPGA
    Stratix® IV E FPGA
    Cyclone® IV GX FPGA
    Cyclone® II FPGA
    Stratix® II FPGAs
    Cyclone® V GX FPGA
    Arria® V GZ FPGA
    Stratix® V GS FPGA
    Stratix® II GX FPGA
    Arria® V GX FPGA
    Cyclone® V GT FPGA
    Cyclone® III FPGAs
    Stratix® V GX FPGA
    Stratix® IV GX FPGA
    Stratix® V GT FPGA
    Intel® Arria® 10 GT FPGA
    Arria® V GT FPGA
    Stratix® III FPGAs
    Intel® Arria® 10 SX SoC FPGA
    Stratix® FPGAs
    Stratix® GX FPGA
    Arria® GX FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Arria® II GX FPGA
    Intel® Arria® 10 GX FPGA
    Arria® II GZ FPGA
    Stratix® IV GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.