Article ID: 000083667 Content Type: Error Messages Last Reviewed: 09/30/2014

Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of '<clock frequency>' on node '<ALTLVDS instance name>pll_fclk~PLL_OUTPUT_COUNTER'

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may get this error when selecting phase shift values for the What is the phase alignment of 'rx_in' with respect to 'rx_inclock' parameter in the ALTLVDS_RX megafunction.  The error occurs when selecting an illegal phase shift value. 

    Due to a bug in the ALTLVDS_RX megafunction, some illegal phase shift values will appear in the megafunction drop-down list. 

    Resolution

    You must select a legal phase shift value in the megafunction, or specify your desired phase shift value in the megafunction variation file. 

    Refer to the related solution below for details on how to calculate legal phase shift values for this parameter. 

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    Intel® Programmable Devices