Article ID: 000083613 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Are the timing violations on the bonding interface of my Cyclone® V or Arria® V DDR3 bonded hard memory controller design valid?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When bonding two DDR3 hard memory controllers in Cyclone® V or Arria® V, you may experience timing violations on the bonding interface. These violations are valid.

Resolution

The workaround is to insert pipeline registers for the bonding signals.

Related Products

This article applies to 10 products

Cyclone® V SE SoC FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA

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