Description
Cyclone and Cyclone II PLLs need to be reset using the areset pin each time
the PLL loses lock. This ensures that the proper phase relationship is kept
between the PLLs outputs. The following text from the Stratix Handbook will
also be added to each of the Cyclone and Cyclone II Handbooks.
The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true:
- PLL reconfiguration or clock switchover enables in the design
- Phase relationships between output clocks need to be maintained after a loss of lock condition