Article ID: 000083540 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is my PLL losing lock during or after performing PLL reconfiguration in my Stratix or Stratix GX device?


  • PLL
    Description If you notice that the PLL is losing lock during or after PLL reconfiguration, one of the reasons could be that the M,N counter settings have changed during the reconfiguration process. If you change the M,N counter or delay element settings in user mode, then the PLL will lose lock. Here is an example:

    Assume your Input clock frequency = 350 MHz and your Output clock frequency = 350MHz

    So, the Quartus II software can choose M=1, N=1 and K=1 to get the above frequency combination.

    Say, you would like to change the output clock frequency to 700MHz and hence change the PLL counters to M=2,N=1 and K=1 to get a output clock frequency of 700MHz. Since you changed the M counter value, to get the desired output frequency, and since the M counter is part of the feedback loop, the PLL will lose lock.

    Also, designers can refer to the Quartus II compilation report - PLL Summary section to see exactly what values the Quartus II software chose for M,N so that these settings are not altered by mistake during PLL reconfiguartion.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs