Assume your Input clock frequency = 350 MHz and your Output clock frequency = 350MHz
So, the Quartus II software can choose M=1, N=1 and K=1 to get the above frequency combination.
Say, you would like to change the output clock frequency to 700MHz and hence change the PLL counters to M=2,N=1 and K=1 to get a output clock frequency of 700MHz. Since you changed the M counter value, to get the desired output frequency, and since the M counter is part of the feedback loop, the PLL will lose lock.
Also, designers can refer to the Quartus II compilation report - PLL Summary section to see exactly what values the Quartus II software chose for M,N so that these settings are not altered by mistake during PLL reconfiguartion.