Article ID: 000083528 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the output pin behavior of my MAX® 7000A/AE/B/S device not match simulation using the Quartus® II software versions 3.0 and below?

Environment

  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description In the Quartus II software version 3.0 and below, there is a problem in the Assembler module which generates incorrect programming files in one exceptional case.

    The problem only occurs in the following situation:

    • The first product term in a macrocell is unused
    • That macrocell is connected in parallel mode with an XOR gate being used to implement a NOR gate with the second product term as an input

    In this case, the Quartus II Assembler does not disable the first product term but allows it to feed the OR gate in the architecture of the MAX devices. Since the product term is unused, the input of the product term is left floating, and that causes the OR gate to be fed with logical 1 instead of logical 0. This behavior causes incorrect outputs.

    This problem has been fixed in the Quartus II software version 4.0.

    Related Products

    This article applies to 1 products

    MAX® 7000A CPLD

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