Article ID: 000083415 Content Type: Troubleshooting Last Reviewed: 05/18/2013

Arria V GZ and Stratix V Hard IP for PCIe IP Core Do Not Cycle through Gen1-Gen3 Data Rates in CBB Testing

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

When performing the TX Eye Test as part of the PCI Express Compliance Base Board (CBB) testing, the Arria V GZ and Stratix V Hard IP for PCIe do not cycle through the Gen1, Gen2, and Gen3 data rates.

Resolution

This issue is fixed in version 13.0 of the Hard IP for PCI Express IP Cores.

Related Products

This article applies to 1 products

Stratix® V FPGAs

1

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