For certain configurations of the DDR3 UniPHY-based memory controller, the
*|pll_c2p_write_clk clock may not be listed in the clocks report during timing analysis. This omission may occur when two of the memory controller PLL counter outputs have the same settings and are merged together. In this case, the
*|pll_c2p_write_clk clock will be merged into the
*|pll_afi_clk which is why it is no longer visible in the TimeQuest reports.
*|pll_c2p_write_clkclock is now associated with