Article ID: 000083268 Content Type: Troubleshooting Last Reviewed: 09/27/2011

The Demonstration Testbench May Fail for Some RapidIO Variations


  • Quartus® II Subscription Edition

    Critical Issue


    RapidIO variations that implement an Input/Output Avalon-MM master or slave Logical layer module and target a Stratix IV GX or Arria II GX device fail simulation with an error message indicating that a signal did not have expected value. The problem is due to an uninitialized RTL parameter in the IP functional simulation model..

    These RapidIO variations cannot simulate successfully with the demonstration testbench.


    To avoid this issue, regenerate your IP functional simulation model with the quartus_map command-line option SIMGEN_RAND_POWERUP_FFS=OFF.

    The following script provides this command for the DUT and the sister RIO in the testbench, for the case of a RapidIO MegaCore function variation that instantiates all modules. To use it to regenerate your IP functional simulation model, update the file names for your variation, modify the commands with the correct device and HDL, and remove the lines that reference modules your variation does not include.

    Run the script, or enter the corresponding commands, in the directory that contains all the source files.

    #!/bin/sh #Modify the following lines with the correct device and HDL information. #Parameter CBX_HDL_LANGUAGE=Verilog or VHDL #Parameter --family is one of {stratixiv, arriaiigx, cycloneiv, arriagx, stratixiigx}. #Regenerate the IP functional simulation model for the DUT: quartus_map --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Verilog,SIMGEN_RAND_POWER_UP_FFS=OFF" --family=stratixiv --source="./rio_rio.v" --source="./rio_riophy_gxb.v" --source="./rio_phy_mnt.v" --source="./rio_riophy_xcvr.v" --source="./rio_riophy_dcore.v" --source="./rio_riophy_reset.v" --source="./rio_concentrator.v" --source="./rio_drbell.v" --source="./rio_io_master.v" --source="./rio_io_slave.v" --source="./rio_maintenance.v" --source="./rio_reg_mnt.v" --source="./rio_transport.v" rio.v #Regenerate the IP Functional Simulation Model for SISTER cp rio_rio_sister.v rio_sister_rio.v cp rio_riophy_gxb_sister.v rio_sister_riophy_gxb.v quartus_map --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Verilog,SIMGEN_RAND_POWERUP_FFS=OFF" --family=stratixiv --source="./rio_sister_rio.v" --source="./rio_sister_riophy_gxb.v" --source="./rio_phy_mnt_sister.v" --source="./rio_riophy_xcvr_sister.v" --source="./rio_riophy_dcore_sister.v" --source="./rio_riophy_reset_sister.v" --source="./rio_concentrator_sister.v" --source="./rio_drbell_sister.v" --source="./rio_io_master_sister.v" --source="./rio_io_slave_sister.v" --source="./rio_maintenance_sister.v" --source="./rio_reg_mnt_sister.v" --source="./rio_transport_sister.v" rio_sister_rio.v

    This issue will be fixed in a future version of the RapidIO MegaCore function.

    Related Products

    This article applies to 3 products

    Arria® II FPGAs
    Stratix® IV FPGAs
    Arria® II GX FPGA