Article ID: 000083267 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the IP compiler for PCI Express not support Max Payload Size (MPS) up to 4096 bytes as specified in the PCIe Specification?



In the market, currently most of the devices supports 256 bytes of MPS or less. Please note that the MPS value used on any PCIe® link must be equivalent to or less than the lowest MPS setting set in either link partner's device capability register (bits [2:0] of Device Capability Register). For instance, if you set the IP Compiler for PCI Express with MPS value of 256 bytes and connected to another PCIe device with a MPS value of 128 bytes, once the system powered up, the root complex will then consider both of these MPS setting of the Device Capability Registers and then write a common MPS value of 128 bytes to each devices' Device Control Register bit [7:5].

You can change the MPS setting for the Device Capability Register through the IP Compiler for PCI Express.

The allowable values are device dependant and are specified in the IP Compiler for PCI Express User Guide.

Related Products

This article applies to 1 products

Stratix® IV GX FPGA