Article ID: 000083196 Content Type: Error Messages Last Reviewed: 12/26/2018

Error(18510): PIPE master channel < ovSOFTPCIE_TxP[x] > can't be placed at the HIP channel location < PIN_xxxx > due to timing requirement.

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error, when compiling the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY in Gen3 PIPE* configurations targetting -2/-3 speed grade Intel® Stratix® 10 devices using the Intel® Stratix® 10 Hard IP for PCI* Express pin locations.

    Resolution

    To work around this problem, either change the transceiver locations to avoid those used by the Intel® Stratix® 10 Hard IP or change the device speed grade to -1.

    This error will be reported when using Intel® Quartus® Prime Pro edition versions 17.0, 17.1and 18.0 when targetting a -2 or -3 speed grade.

    This error has been fixed starting in Intel® Quartus® Prime Pro edition version 18.1.

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