Article ID: 000083193 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why can't I select segmented mode as a buffer acquisition mode in the SignalTap II logic analyzer?


  • Quartus® II Subscription Edition

    Segmented buffers are not supported when you create the SignalTap® II logic analyzer using the MegaWizard® Plug-In Manager in the Quartus® II software version 7.2, and the Segmented Buffer checkbox option is disabled in the SignalTap II user interface.

    This problem is fixed begining with the Quartus II Software version 8.0.

    In the Quartus II software versions 7.1 and earlier, you can select Circular or Segmented Mode as a buffer acquisition mode in the SignalTap II logic analyzer interface even if you created the Signaltap II instance using the MegaWizard Plug-In Manager . 

    To enable a segmented buffer, edit the SignalTap II MegaWizard-generated wrapper file (<instance name>.v|vhd) and SignalTap II file (<name>.stp) by following these steps:

    1. In the SignalTap II MegaWizard-generated wrapper file make the following changes:
      • For VHDL
        • In the component declaration, add the generic parameter SLD_SEGMENT_SIZE : NATURAL;
        • In the instantiation, set the SLD_SEGMENT_SIZE parameter to the number of samples per segment.
      • For Verilog HDL
        • Add the following attribute: sld_signaltap_component.sld_segment_size = <segment size>
    2. Save and close the wrapper file.
    3. Compile the project.
    4. On the File menu, point to Create/Update and click Create SignalTap II File from Design Instance(s).
    5. Save and close the SignalTap II file.
    6. In a text editor, open the newly-created SignalTap II file.
    7. Locate the trigger tag which is similar to this: <trigger CRC="my_value" name="my_name">.
    8. Add two new attributes to the element defined by the trigger tag: segment_size="<segment size>" and  trigger_type="segmented". It should look similar to this: 
      <trigger CRC="my_value" name="my_name" segment_size="32" trigger_type="segmented">
    9. Save and close the SignalTap II file.
    10. Program the device and run the SignalTap II analysis.

    Related Products

    This article applies to 1 products

    Stratix® II FPGAs



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