Article ID: 000083130 Content Type: Troubleshooting Last Reviewed: 06/14/2016

Why does PCI Express link training fail intermittently ?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug, you may see link training failure with the Hard IP for PCI Express® IP Core due to the transmission of corrupted TS1s.

    The Hard IP core LTSSM state cycles between the Detect and Polling.Config state. Due to the corrupted TS1s the link partner can only proceed to the Polling.Active state, causing link training to fail.

    Resolution

    Modify the IP to use the soft reset controller, please refer to the related solution below:

    This issue is fixed in v13.1.2 and later of the the Quartus® II software.

    Related Products

    This article applies to 8 products

    Arria® V GT FPGA
    Arria® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA

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