Article ID: 000083090 Content Type: Troubleshooting Last Reviewed: 05/10/2018

Why do I see hold time violations in the Low Latency 40G Ethernet Intel® FPGA IP core, when KR4 is enabled?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 40G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Critical Issue

    Description

    Due to a problem with the Low Latency 40G Ethernet Intel® FPGA IP core on Intel® Stratix® 10, you may see minor hold time violations when the KR4 feature is enabled. 

    Resolution

    A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software. 

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