Article ID: 000083083 Content Type: Troubleshooting Last Reviewed: 03/15/2019

Why does the Transceiver TX simplex sends wrong data when the CMU PLL of PCIEx1 (HIP) is located at the same channel?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with Intel® Arria® V and Intel Cyclone® V devices, the transmitter in TX Only mode may output incorrect data if the CMU PLL of a PCIex1 with Hard IP is located in the same transceiver channel. The transmitter in TX Only mode and the CMU PLL of a PCIex1 with Hard IP cannot be placed together at transceiver channel 1 or 4. 

    Resolution

    There is no workaround for this problem. Starting from Intel® Quartus® Prime Standard version 18.0, user will receive the following error message when the CMU PLL of a PCIex1 with Hard IP is located in the same channel as  transmitter in TX Only mode.

    Error (20039): TX channel < tx_pin~CLUSTER~HSSI_TX_CHANNEL_CLUSTER1 > and PCIE pll can't share the same duplex channel location

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs

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