Why does the Transceiver TX simplex sends wrong data when the CMU PLL of PCIEx1 (HIP) is located at the same channel?

Due to a problem with Intel® Arria® V and Intel Cyclone® V devices, the transmitter in TX Only mode may output incorrect data if the CMU PLL of a PCIex1 with Hard IP is located in the same transceiver channel. The transmitter in TX Only mode and the CMU PLL of a PCIex1 with Hard IP cannot be placed together at transceiver channel 1 or 4. 

There is no workaround for this problem. Starting from Intel® Quartus® Prime Standard version 18.0, user will receive the following error message when the CMU PLL of a PCIex1 with Hard IP is located in the same channel as  transmitter in TX Only mode.

Error (20039): TX channel < tx_pin~CLUSTER~HSSI_TX_CHANNEL_CLUSTER1 > and PCIE pll can't share the same duplex channel location