In CPRI RE slaves, the transceiver PLL reference clock is not connected correctly.
This issue prevents the RE slave from completing link negotiation successfully in Arria V and Stratix V devices.
To fix this problem in your CPRI RE slave instance that targets an Arria V or Stratix V device, you must edit the <project name>_002.v file after you generate your CPRI instance. In a text editor, perform the following substitutions:
- In the connection to the Rx transceiver (
pll_ref_clk (inst_cpri_phy_pll_inclk_clk)with the new text
- In the connection to the Tx transceiver (
pll_ref_clk (inst_cpri_phy_pll_ref_clk_clk)with the new text
This issue is fixed in version 12.1 of the CPRI MegaCore function.