Article ID: 000083071 Content Type: Troubleshooting Last Reviewed: 05/20/2013

Incorrect Transceiver Reference Clocks in CPRI IP Core RE Variations

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In CPRI RE slaves, the transceiver PLL reference clock is not connected correctly.

    This issue prevents the RE slave from completing link negotiation successfully in Arria V and Stratix V devices.

    Resolution

    To fix this problem in your CPRI RE slave instance that targets an Arria V or Stratix V device, you must edit the <project name>_002.v file after you generate your CPRI instance. In a text editor, perform the following substitutions:

    • In the connection to the Rx transceiver (inst_rx_xcvr), replace pll_ref_clk (inst_cpri_phy_pll_inclk_clk) with the new text pll_ref_clk (inst_cpri_phy_pll_ref_clk_clk).
    • In the connection to the Tx transceiver (inst_tx_xcvr) replace pll_ref_clk (inst_cpri_phy_pll_ref_clk_clk) with the new text pll_ref_clk (inst_cpri_phy_pll_inclk_clk).

    This issue is fixed in version 12.1 of the CPRI MegaCore function.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs

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