Critical Issue
Due to a problem in the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express, automatic RX polarity inversion during link training is not supported. When the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express core receives TS2 training sequences during the Polling.Config state, automatic lane RX polarity inversion is not guaranteed. The link may train to a smaller than expected link width or may not train successfully. This problem can affect configurations with any PCIe* speed and width.
To address this problem, Intel® has created an RX polarity inversion soft logic IP that performs automatic polarity inversion during link training.
When you enable this RX polarity inversion soft logic, automatic polarity inversion is available for all PCIe* configurations except for Gen1 x1.
This RX polarity inversion soft logic fix does not support CvP or autonomous mode because the core fabric needs to be programmed for the soft logic IP to work.
- Open the Intel Arria 10 Hard IP for PCI Express GUI
- Select the PHY Characteristics tab
- Right click on the Intel Arria 10 Hard IP for PCI Express banner and select Show Hidden Parameters
- Scroll down until you see the Enable rx_polarity inversion soft logic parameter and select it
- Do not modify any other hidden parameters
- Right click on the Intel Arria 10 Hard IP for PCI Express banner and select Hide Hidden Parameters (optional but recommended)
- Select Generate HDL