Article ID: 000082953 Content Type: Product Information & Documentation Last Reviewed: 12/11/2018

How do I enable the RX polarity inversion soft logic of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express, automatic RX polarity inversion during link training is not supported.  When the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express core receives TS2 training sequences during the Polling.Config state, automatic lane RX polarity inversion is not guaranteed.  The link may train to a smaller than expected link width or may not train successfully.  This problem can affect configurations with any PCIe* speed and width.

    To address this problem, Intel® has created an RX polarity inversion soft logic IP that performs automatic polarity inversion during link training.

    When you enable this RX polarity inversion soft logic, automatic polarity inversion is available for all PCIe* configurations except for Gen1 x1.

    This RX polarity inversion soft logic fix does not support CvP or autonomous mode because the core fabric needs to be programmed for the soft logic IP to work.

    Resolution
    Beginning with Intel® Quartus® Prime software version 15.1.1 and up to but not including version 17.1, the RX polarity inversion soft logic option is hidden in the PHY Characteristics tab of the Intel Arria 10 Hard IP for PCI Express GUI.  From Intel® Quartus® Prime software version 17.1 and later, this RX polarity inversion soft logic option is natively visible in the GUI.
     
     
     Instructions to enable the hidden RX polarity inversion soft logic option.
    1. Open the Intel Arria 10 Hard IP for PCI Express GUI
    2. Select the PHY Characteristics tab
    3. Right click on the Intel Arria 10 Hard IP for PCI Express banner and select Show Hidden Parameters
    4. Scroll down until you see the Enable rx_polarity inversion soft logic parameter and select it
    5. Do not modify any other hidden parameters
    6. Right click on the Intel Arria 10 Hard IP for PCI Express banner and select Hide Hidden Parameters (optional but recommended)
    7. Select Generate HDL

     

     

     

     

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs