Article ID: 000082952 Content Type: Troubleshooting Last Reviewed: 12/05/2018

Why does the Ethernet 10G MAC Intel® FPGA IP's XGMII interface output last few bytes of data with unknown state in simulation?

Environment

  • Cyclone® IV FPGAs
  • Cyclone® V FPGAs and SoC FPGAs
  • Arria® V FPGAs and SoC FPGAs
  • Stratix® IV FPGAs
  • Stratix® V FPGAs
  • Arria® II FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet 10G MAC Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may encounter above problem if the csr_reset signal of Ethernet 10G MAC Intel® FPGA IP did not toggle once after the start of simulation.

    Resolution

    To work around this problem, the csr_reset signal needs to be toggled once at the beginning of simulation.