Article ID: 000082942 Content Type: Troubleshooting Last Reviewed: 02/26/2014

What is the voltage diagram for the Schmitt trigger input standard and how does it relate to VIL and VIH specifications?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

A  Schmitt trigger input standard allows input buffers to respond to slow input edge rates with a fast output edge rate. Most importantly, Schmitt triggers provide hysteresis on the input buffer, preventing slow-rising noisy input signals from ringing or oscillating on the input signal driven into the logic array.

The following voltage diagrams illustrate the difference between the Schmitt trigger input standard and the LVTTL/LVCMOS input standard, and how Vschmitt relates to VIH and VIL.

Figure 1. LVTTL/LVCMOS Input Standard Voltage Diagram

Figure 2. Schmitt Trigger Input Standard Voltage Diagram

 

Related Products

This article applies to 3 products

MAX® V CPLDs
MAX® II Z CPLD
MAX® II CPLDs

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