Article ID: 000082879 Content Type: Troubleshooting Last Reviewed: 02/05/2015

Why do I see setup time violation on my I/O paths in the Quartus II software version 13.0 SP1?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see setup time violations on your I/O paths that use Hard Memory Controller (HMC) pins as I/O pins on Cyclone® V devices in the Quartus® II software version 13.0 SP1. I/O signals that use HMC pins are routed using HMCPHY_RE routing elements have a significantly higher routing delay compared to other pins. These routing delays are part of the Cyclone V timing models in the Quartus II software version 13.0 SP1 and were not included in earlier timing models.

    Resolution

    Avoid using HMC DQ pins as the input pin for high-speed signals.

    Avoid using HMC DQ  and command pins as the output pin for high-speed signals.

    You can refer to HMC Pin column of Cyclone V device pin-out files to identify the HMC pins of your targeted device.

    Related Products

    This article applies to 6 products

    Cyclone® V GT FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V GX FPGA
    Cyclone® V E FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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