Article ID: 000082822 Content Type: Troubleshooting Last Reviewed: 01/07/2019

Why is the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GE/25GE Design Example Held in Reset?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GE/25GE Example Design, the ethernet circuit is held in reset at startup and the link will not come up.

    Resolution

    To work around this problem, manually disable the reset by opening the example design in-system sources and probes and set source bits [3:1] to 3'b111.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition.

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