Article ID: 000082821 Content Type: Troubleshooting Last Reviewed: 11/28/2024

Why does the Low Latency 100G Ethernet Stratix® 10 FPGA IP show 'H-Tile' as 'Target transceiver tile' when targeting a 'L-Tile' only device?

Environment

    Intel® Quartus® Prime Pro Edition
    Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When working with a 'L-Tile' only device, the 'Target transceiver tile' drop down menu is disabled and shows the 'H-Tile' default value. 'H-Tile' is coded in the component description file as its default.

Resolution

The designer can safely ignore the 'H-Tile' as 'Target transceiver tile' when targetting L-Tile devices, the IP will generate HDL targeting the correct device tile. This problem will be fixed in a future release of the Quartus® Prime Software.

Related Products

This article applies to 3 products

Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 SX SoC FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.