Article ID: 000082818 Content Type: Product Information & Documentation Last Reviewed: 12/17/2018

How do I access the Intel® Stratix® 10 Hard IP for PCI Express* IP Core configuration space registers without the Local Management Interface?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Local Management Interface (LMI) is not supported in the Intel® Stratix® 10 Hard IP for PCI Express* IP Core. You can access the Intel® Stratix® 10 Hard IP for PCI Express* IP Core configuration space register via the Hard IP Reconfiguration Interface. 

     

    Resolution

    To access the Hard IP Reconfiguration block, IP Catalog >> Avalon®-ST Intel® Stratix® 10 Hard IP for PCI Express* OR Avalon®-MM Intel® Stratix® 10 Hard IP for PCI Express*>> "Configuration, Debug and Extension Options" tab >> turn on "Enable hard IP dynamic reconfiguration of PCIe read-only registers". To dynamically modify the value of configuration registers that are read-only at run time, refer to the "Hard IP Reconfiguration" section of the respective user guide.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.