Why do I see Setup timing violations on my Cyclone V HPS SDRAM to FPGA Core paths?

To improve the timng of the Cyclone® V HPS SDRAM to FPGA Core paths you can try overconstraining the paths in question using the assignment below:

if {$::quartus(nameofexecutable) == "quartus_fit"} {
set_max_delay -from [get_keepers *<instance>\|fpga_interfaces\|f2sdram~FF_*] -to [get_keepers <core registers>] <value>
}

The specific <instance> and <core registers> names will need to be modified to match your design structure.
Note that this assignment only overconstrains the paths during the fitting process and that the timing analysis performed in the TimeQuest Timing Analyzer will be valid.

The value to overconstrain by depends on the magnitude of your timing violations.

For example:

If your default setup relationship is 6ns and you have a worst case negative slack on these paths of -1ns then applying a set_max_delay value of 4.5ns is reasonable.

Or if your default setup relationship is 4ns and you have a worst case negative slack on these paths of -100ps then applying a set_max_delay value of 3.5ns is reasonable.

This problem is scheduled to be fixed in a future release of the Quartus® II software.